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Review Chap 3

  • Transistor: MOS transistors, which are below our lowest level of abstraction. Transistor has three terminals: the gate, the source and the drain.

  • Two types of MOS: P-type, when the gate is supplied with 0 volts, it acts as a piece of wire(short circuit), when supplied with 1.2 volts, it acts like an open circuit; N-type, which is opposite to P-type. when there are no volts, it acts like an open circuit, when there are 1.2 volts in the gate, it acts like a piece of wire(short circuit).

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    在使用上，N 管和 P 管的使用方向是反过来的，并且在充当开关时，一般以 N 管作下管，P 管做上管，主要原理参考这篇文章。可以发现，在简化图中看不出哪头是源极哪头是漏极，只在 Gate 处加了一个非来表示，但是实际上两个的使用方向大概是相反的（例如下图）

Logic Gates

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• 可以发现，与或门的设计都是从与非和或非开始的，而其结构的上半部分是一个“或”选择高电势的关系，下半部分是“与”选择接地的关系，深入感受一下这一层，就会发现这些电路都很好设计。

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Also, you can consider using gates with more than two inputs, whose truth table can be easy to draw.

Combinational Logic Circuits

1.Decoder

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  • Exactly one of its outputs is 1 and all the rest are 0s.
  • In general, decoders have n inputs and 2^n outputs.
  • We say the output line that detects the input pattern is 🔗asserted.
  • The decoder is useful in determining how to interpret a bit pattern.
  • Mux(multiplexer): to select one of the inputs and connect it to the output.

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  • The select signal (S in Figure 3.12) determines which input is connected to the output.
  • We say S selects the source of the mux (either A or B) to be routed through to the output C.
  • In general, a mux consists of 2^n inputs and n select lines.
  • 用来实现输入的路由，有点像铁轨的变道装置，通过 S 的数据来选择使用哪一条输入。
  • One-Bit Adder (Full Adder)

The truth table of it is below.

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  • It describes the result of binary addition on one column of bits within two nbit operands.
  • Aj and Bj are digits from inputs,Cj is the carry number from Aj-1 + Bj-1 , and Sj is the (j+1)th digit of output.

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如果不考虑进位的话，这是一个半加器；（如图中最右边）考虑进位的话，这是一个全加器（如其他部分）。

  1. The Programmable Logic Array(PLA) in Chinese:可编程阵列
  2. The implementation algorithm is simply to connect the output of an AND gate to the input of an OR gate if the corresponding row of the truth table produces an output 1 for that output column. Hence the notion of programmable. That is, we say we program the connections from AND gate outputs to OR gate inputs to implement our desired logic functions.
  3. Logical Completeness

We say that the set of gates {AND, OR, NOT} is logically complete because we can build a circuit to carry out the specification of any truth table we wish without using any other kind of gate.

Basic Storage Elements

R-S Latch

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R-S latch can store a bit of information. And the circuit is above.

  • R : Resetting : setting the latch to store a 0;
  • S : Setting: setting the latch to store a 1;
  • The Quiescent (or quiet) State: the state when the latch is storing a value, either 0 or 1 and nothing is try to change the value.
  • When inputs S and R both have logic value 1.
  • At this time, the output of a and b won't change. (But a and b are the opposite if we set S and R properly.)
  • Setting the Latch to a 1 or a 0
  • The latch can be set to a 1 by momentarily setting S to 0.
  • The latch can be set to a 0 by momentarily setting R to 0.
  • Both S and R must never be allowed to be set to 0 at the same time.

The Gated D Latch

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WE stands for write enable.When it is not asserted, the output S and R are both equal to 1. When it is momentarily set to 1,exactly one of the outputs(S or R) are set to 0,depending on the values of D.

D=1—>S=0 D=0—>R=0 WE=0—>S=R=1

The Concept of Memory

Memory is made up of a number of locations, each uniquely identifiable and each having the ability to store a value.We refer to the unique identifier associated with each memory location as its address. And the number of bits of information stored in each location as its addressability.

  • Address Space : the total number of uniquely identifiable locations.
  • Addressability : 注意和 address space 做区分，address space 指的是 memory 中，依据寻址输入（下图的A[1:0]）能够查询到的 location 数量的上限（即两条线但是只画出了 3个location的话，address space 依然是 4）。
  • A 2^2-by-3-Bit Memory

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▪ 左侧的 decoder 解析A[1:0]中传入的 location 信息，然后将该信息输入到 mux 中，以选择路由对应的 location 信息。

▪ That is, the memory has an address space of four locations and an addressability of three bits. It requires two bits to specify the address.

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Sequential Logic Circuits

  • Can both process information and store information.

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  • Sequential logic circuits are used to implement a very important class of mechanisms called finite state machines, which are used in essentially all branches of engineering.
  • e.g: used as controllers of electrical systems, mechanical systems, and aeronautical systems.

An Example: The Combination Lock

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  • Lock (a) will only open when you complete dialing in a specific order. Assume that the correct order is R13-L22-R3.
  • Lock (b) won't care about how you complete rotation.

The Concept of State

State: is a snapshot of all the relavent elements of the system at the moment the snapshot is taken.

  • A finite state machine consists of five elements:
  • a finite number of states;
  • a finite number of external inputs ;
  • a finite number of external outputs;
  • an explicit specification of all state transitions;
  • an explicit specification of what determines each external output value;
  • There is no fixed amount of time between successive inputs to the finite stat machine above. We say these systems are asynchronous because there is nothing synchronizing when each state transition must occur.
  • Synchronous Finite State Machine: the state transitions take place, one after the other, at identical fixed units of time.

Attention: Whether it is synchronous or not,they carry out work,one state transition at a time, moving closer to a goal.

  • The Clock: Control of that synchronous behavior is in part the responsibility of the clock circuit. Each of the repeated sequence of identical intervals is referred to as a clock cycle.

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The Flip-Flop

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▪ The storage elements that allow us to read the current state throughout the current clock cycle, and not write the next state values into the storage elements until the beginning of the next clock cycle.

  • Reading must be allowed throughout the clock cycle, and writing must occur at the end of the clock cycle.
  • The master / slave flip-flop can be constructed out of two gated D latches, one referred to as the master, the other referred to as the slave.
  • Think about that: When master is "reading", the slave is "writing", and vice versa.
  • FF 的行为在一个 Clock Cycle 里完成，在分析不同维度的事情的时候要从不同维度的角度来思考。
  • 更底层的：
  • 假设 Cycle 的前半部分 Master 可写， Slave 只读，则：
  • 在模式切换的那一瞬间，Master 写入的数据会被 Slave 存储；
  • 更抽象的：
  • 在 Cycle 开始结束后，会输出 Cycle 进行时输出的数据；

The Preview of Datapath in LC-3

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  • The data path consists of all the logic structures that combine to process information in the core of the computer.
  • A register is simply a set of n flip-flops that collectively are used to store one n bit value.
  • In the figure, PC, IR, MAR, and MDR are all 16-bit registers that store 16 bits of information each. The block labeled REG FILE consists of eight registers that each store 16 bits of information.
  • The data path also shows three 1-bit registers, N, Z, and P.